Logic synthesis is well known in the integrated circuit design arts. Logic synthesis is the process of transforming a register-transfer level (RTL) description of a circuit into an implementation consisting of a set of interconnected gates. During this process logically equivalent memory elements can be implemented using different design elements in order to meet necessary constraints.
An example prior art original circuit design is shown in FIG. 1A. The circuit, generally referenced 10, comprises AND gate 12 and a memory element 14 which may comprise a latch, register, flip-flop, etc. The circuit directly implements Verilog code “always @(posedge clk) Q <=A & B;” which implements the logic functionQ=A & B
A second example prior art original circuit design is shown in FIG. 1B. The circuit, generally referenced 20, comprises NOT gates 22 and 24, OR gate 26 and memory element 28.
The circuit implements Verilog code “always @(posedge clk) Q<=!(A|B);” which implements the logic functionQ=!(!A|!B)which is functionally equivalent toQ=A & B
Due to the increased density of modern integrated circuits (ICs), the amount of power consumed by modern ICs continues to escalate. In response, there has been an increasing focus to lower the power consumption of new digital hardware circuits. One approach to reducing power consumption is to employ so called clock gating, a technique which manufacturers have incorporated into the automated design of digital hardware circuits.
Clock gating is a well known technique used to reduce the power consumption of digital hardware circuits. It is often employed as one of several power saving techniques typically applied to synchronous circuits used in large microprocessors and other complex circuits. To save power, clock gating solutions add additional logic to a circuit to modify the functionality of the clock input of a flip-flop or latch, thereby disabling portions of the circuitry where flip-flops or latches do not change state.
An example prior art original circuit design without any clock gating applied is shown in FIG. 2A. The circuit, generally referenced 30, comprises logic cloud 32, multiplexer 34 and memory element 36. In the circuit, the CLK signal is input directly into memory element 36, and the inputs to the multiplexer comprise the output Q1 from the memory element, signal I from logic cloud 36 and the EN signal. This circuit implements the logic functionIf (EN) then I else (Keep Old Value)
An example prior art circuit design of a clock gated circuit of FIG. 2A is shown in FIG. 2B. The circuit, generally referenced 40, comprises logic cloud 42, AND gate 44 and memory element 46. In this circuit, the EN and CLK signals are input to AND gate 44, whose output is the input of memory element 46. This circuit also implements the logic functionIf (EN) then I else (Keep Old Value)
When analyzing the circuits shown in FIGS. 2A and 2B, viewing the data and the clock inputs separately (as is done in logic synthesis today), memory elements 36 and 46 appear to have different functionality, because the data input of 36 has different functionality that the data input of 46, and the clock inputs differ as well. By considering the entire logic circuits as a whole, it is evident that both implement the aforementioned identical logic function. Considering entire logic circuits as a whole enables many logic transformations and optimizations that are not possible otherwise.
Current synthesis tools generally do not allow changing the number of memory elements used to implement a design. Therefore, the synthesis tool does not attempt to locate identical memory elements (latches or flip-flops) in order to remove duplicates. With the recent widespread acceptance of clock gating as a viable design technique, synthesis tools are freer to add or remove flip-flops or latches. Since synthesis tools are now freer, it is logical that they search for redundant memory elements, that is, two or more memory elements that have the exact same function. When clock gating is not implemented, synthesis tools can locate redundant memory elements by comparing the function of the input pins. Under clock gating, however, it does not suffice to compare the inputs. Under clock gating, the data and clock inputs may be different, but the functionality of the memory elements can still be identical, depending on the clock gating function.